1. Field of the Invention
The present invention relates to a semiconductor device having a DRAM of excellent data retention characteristics and with less scattering of threshold voltage of an MISFET in a memory cell, as well as a method of manufacturing such a semiconductor device.
2. Description of the Related Art
One of most important technical subjects in DRAM is how to retain static charges (data) stored in capacitors for a long time. The charge leak path mainly includes the following three routes. That is, they include pn-junction that is connected to one side of a capacitor, a channel region of the MISFET in the memory cell and capacitor itself.
While miniaturization of devices has been progressed with an aim of increasing the integration degree and saving power consumption in DRAM, it results in lowering of a threshold voltage of the MISFET in the memory cell due to the short channel effect. When the threshold voltage lowers, it leads to a significant problem of leakage of charges due to the sub-threshold leak.
As a method of controlling the threshold voltage of the MISFET in the memory cell several methods have been proposed. For example, Japanese Patent Laid-open No. 8-330439 proposes a method of implanting impurities having a conduction type similar to that of a semiconductor substrate, thereby controlling the threshold voltage. To increase the threshold voltage to such a level as not resulting in the problem of the sub-threshold leak, the impurity concentration at the surface of the semiconductor substrate has to be increased to a level as high as 1018 cm−3 or more.
However, this forms a pn-junction between a diffusion region and the channel that high electric field resulting in a problem of increasing the leakage of static charges by the pn-junction leak. As described above, the countermeasure for the prevention of the sub-threshold leakage is in a trade off relation with increase of the pn-junction leak.
As a counter measure for solving the problem described above, Japanese Patent Laid-open Nos. H10-56147 and 2000-236074 describe structures in which the distribution of impurities in the diffusion region is asymmetrical. The structure is hereinafter referred to as an asymmetrical diffusion region structure.
The method described in Japanese Patent Laid-open No. H10-056147 has a feature of implanting impurities (for example, boron ions) having a conduction type identical with that of the channel only to the diffusion region on the side of a data line, thereby increasing the threshold voltage of the MISFET in the memory cell. The sub-threshold leak is suppressed by increasing the threshold voltage. Further, since the concentration of the impurities on the side of the capacitor is not increased, it is possible to decrease the pn-junction leak on the side of the capacitor that causes charge leakage compared to the case that impurities are implanted symmetrically, and improve the charge retention characteristics.
However, this method causes increase of the implantation dose of the impurities introduced on the side of the data line for the control of the threshold voltage of the MISFET in the memory cell. This consequently causes offset between the gate electrode and the diffusion region region on the side of the data line. In this case, offset means that an overlap region between the gate electrode of the MISFET and the diffusion region of the dataline side disappears. Then, with an aim of preventing the offset, a method of introducing impurities of a conduction type identical with that of the channel region and impurities of a conduction type identical with that of the diffusion region only on the side of the data line has been proposed by the technique described in JP-A No. 2000-236074.
However, as a result of the study on the asymmetrical diffusion region structure made by the present inventor, it has been found that this results in a problem of increasing the scattering of the threshold voltage of the MISFET in the memory cell. Depending on the implantation condition of the impurity ions introduced on the side of the data line, the scattering (variation) of the threshold voltage reaches twice as large as that in the usual (symmetrical) structure.
When the threshold voltage is excessively low, sub-threshold leak occurs to cause leakage of charges stored in the capacitor. On the other hand, when the threshold voltage increases excessively, introduction of charges to the capacitor through the MISFET becomes insufficient to cause insufficiency in information writing. Increase of scattering of the threshold voltage means increase in the number of defective bits, which results in lowering of yield.
The result of the simulation study on the cause of the scattering of the threshold voltage of the MISFET in the memory cell is to be described. FIG. 2 and FIG. 3 show how the scattering of the shape at the periphery of a gate electrode gives an effect on the scattering of the threshold voltage. The parameters taken into consideration here are a gate length, inclination of a gate electrode (gate taper angle), a gate oxide film thickness, oxide film thickness for gate electrode side wall, a through oxide film thickness, a side wall spacer film thickness and reduction of tungsten silicide gate during oxidation, which are schematically shown in FIG. 2.
After forming a gate oxide film 20 comprising a silicon oxide film by thermal oxidation on a semiconductor substrate 1, a polycrystalline silicon film 21, a tungsten silicide film 22, and a silicon nitride film 23 are deposited successively. Then the silicon nitride film 23, the tungsten silicide film 22 and the polycrystalline silicon film 21 are delineated by dry etching successively each into a desired gate length by using a photoresist pattern as a mask to form a gate electrode 27. Heat treatment in an oxidation atmosphere (light oxidation treatment) is applied to form a gate electrode side wall oxide film 24 and a through oxide film 25. Then a sidewall spacer 26 comprising a silicon nitride film is formed on the side wall of the gate electrode 27 by a CVD method. The gate length is a length of the polycrystalline silicon gate electrode. Scattering in each of the gate length, the inclination of the gate electrode (gate taper angle) and the retrogression amount of tungsten silicide are mainly caused in the dry etching step upon forming the gate electrode 27. Further, scattering in the thickness of the gate electrode side wall oxide film 24 and the through oxide film 25 is caused mainly in the light oxidation step. The scattering in the thickness of the side wall spacer 26 is caused in the step of forming the side wall spacer 26. Ion implantation of impurities are conducted appropriately in two steps just after light oxidation and just after forming the side wall spacer.
FIG. 3 shows the percentage of the scattering in each shape for the total amount of the scattering of the threshold voltage in comparison between a usual structure and the asymmetrical diffusion region structure. Scattering of the shape results in the scattering of the distribution of impurities implanted in a semiconductor substrate and this fluctuates the threshold voltage of the MISFET. It can be seen that the effect of the scattering of the gate length is large in the usual structure, whereas the effect of the scattering in the thickness of the gate electrode side wall oxide film 24 is large in the asymmetrical diffusion region structure. When the gate length is as small as about 0.1 μm, the short channel effect becomes larger to increase the effect of the scattering of the gate length on the threshold voltage in the usual structure. On the contrary, it is considered that in the asymmetrical diffusion region structure, since impurity ions of a conduction type identical with that of the channel are implanted on the side of the data line, the short channel effect is decreased.
In the case of the asymmetrical diffusion region structure, boron ions and arsenic ions, for example, are implanted only to the diffusion region on the side of the data line at a position apart from the gate electrode by thickness of the gate electrode side wall oxide film. The threshold voltage is highly sensitive to the distribution of the impurities. When the concentration of boron is excessively high, this likely results in offset to increase the threshold voltage. When the concentration of arsenic is excessively high, the threshold voltage is lowered by the short channel effect. Since the scattering in the thickness of the gate electrode side wall oxide film changes the distribution of the impurities, the threshold voltage varies greatly. Accordingly, in order to decrease the scattering of the threshold voltage in the asymmetrical diffusion region structure, it is important to control the scattering of the thickness of the gate electrode side wall oxide film.
The gate electrode side wall oxide film 24 is formed in a so-called light oxidation. Light oxidation is a treatment of thermally oxidizing a semiconductor substrate again after the fabrication of a gate electrode with an aim of removing etching damages in the substrate at the gate edge upon fabrication of the gate electrode. This is an indispensable step for providing a semiconductor device with high reliability. While the gate electrode 27 is formed as a stacked structure of a polycrystalline silicon film 21 with addition of impurities and a tungsten silicide film 22, those portions where the films are exposed (lateral side of the gate electrode) are also oxidized simultaneously in the light oxidation.
The following two reasons may be considered for the scattering of the thickness of the gate electrode side wall oxide film formed by light oxidation.
The first is the dependence of the oxidation speed on the impurity concentration. In the polycrystalline silicon film 21, impurities, for example, phosphorus are added with aim of lowering the resistance. It has been known that the oxidation speed for polycrystalline silicon with addition of impurities such as phosphorus is increased by about 1.5 to 6 times compared with that for polycrystalline silicon with no addition of impurities. Accordingly, as the concentration of the impurities in the polycrystalline silicon is different, the oxidation speed differs correspondingly. This is one of the factors of causing scattering in the thickness of the gate electrode side wall oxide film.
The other is the dependence of oxidation speed on the crystal face orientation. The oxidation speed of the silicon crystal is different depending on the crystal face. For example, the (111) crystal face of silicon has an oxidation speed twice as high as the (100) crystal face. In the polycrystalline silicon used for the gate electrode, since crystal grains having various crystal face orientations are present, they cause scattering in the thickness of the side wall oxide film.
As described above, to decrease the scattering of the threshold voltage of the MISFET in the memory cell in the asymmetrical diffusion region structure, it is necessary to decrease the scattering of the thickness of the gate electrode side wall oxide film. However, since the gate electrode is formed of polycrystalline silicon with addition of impurities and the oxidation speed is different depending on the concentration of impurities and the orientation of crystal grains, scattering in the thickness of the oxide film formed to the gate electrode side wall is increased inevitably.